This invention relates generally to the field of semiconductor devices and more particularly to an SRAM memory cell with reduced coupling between the bodies of pass transistor and drive transistor and method.
Modern electronic equipment such as televisions, telephones, radios and computers are generally constructed of solid state devices. Integrated circuits are preferred in electronic equipment because they are extremely small and relatively inexpensive. Additionally, integrated circuits are very reliable because they have no moving parts but are based on the movement of charge carriers.
Integrated circuits may include transistors, capacitors, resistors and other semiconductor devices. Typically, such devices are fabricated on a substrate and interconnected to form power supplies, memory arrays, logic structures, timers and other components of an integrated circuit. One type of memory array is a static random access memory (SRAM) in which memory cells are continuously available for reading and writing data.
SRAMs have traditionally been fabricated with CMOS technology. However, more recently, SRAMs have been fabricated with silicon-on-insulator (SOI) technology. An SRAM cell consists of a pair of cross-coupled inverters and a pair of access transistors, pass gates or pass transistors. These pass transistors couple the bit-lines or data-lines to the output of the inverters. The output of the first inverter is connected to the input of the second inverter and the output of the second inverter is connected to the input of the first inverter. Typically an inverter consists of a p-channel pull-up or load transistor and an n-channel pull-down or driver (or drive) transistor. The sources of the load transistors are coupled to the positive terminal of a supply voltage, Vdd. The sources of the driver transistors are coupled to the negative terminal of the supply voltage, Vss.
One prior art SOI SRAM memory cells uses partial trenches to connect to the bodies (silicon under the channel regions) of the driver and pass transistors to the Vss terminal. Use of a partial-trench results in relatively high resistance between the body of a transistor and low resistance active region used to couple to the Vss terminal (Vss contact) because the region that connects the two is very thin. It is thinner than the silicon in the channel region, is buried under field oxide used to isolate transistors, and is located over the back-side (buried) oxide. The partial-trench silicon is also lightly doped, typically with levels equal to or less than the channel doping level. Only the region under the Vss contact with a small overlap to provide for mis-alignment tolerance uses thicker silicon corresponding to that of the active region and has relatively higher doping level corresponding to that of the source/drain (S/D) implant levels to reduce contact resistance. This region is typically silicided in modern day circuits. Partial trench and partial trench isolation region are interchangeably used below.
In an SOI SRAM cell, in order to keep the SRAM cell size to a minimum, typically only one Vss contact is provided for both pass and driver transistor bodies. In one such prior art cell the Vss contact is placed to the side of the driver transistor on the side farther away from the pass transistor. The distance between the pass transistor body region and the Vss contact is greater than the distance between the driver transistor body region and the Vss contact. The distance between the pass transistor body region and the Vss contact is also greater than the distance between the bodies of the pass transistor and driver transistor. This architecture results in a larger resistance between the pass gate body region to the Vss contact than the resistance between the pass gate body region to the drive transistor body and causes large coupling between pass and drive transistor bodies, which reduces static noise margin for an SRAM cell for partial trench designs.
In accordance with the present invention, a memory cell with reduced coupling between pass transistor and driver transistor bodies and method are provided that substantially eliminate or reduce disadvantages and problems associated with previously developed systems and methods.
According to one embodiment of the present invention, a semiconductor structure includes an SOI memory cell having a pass transistor having a body and a driver transistor having a body. The SOI memory cell also includes a source voltage contact coupling the bodies of the pass transistor and the driver transistor and a non-square conductive active region coupled to the source voltage contact. The shortest distance between the body of the pass transistor and the source voltage contact is greater than the shortest distance between the body of the pass transistor and the body of the driver transistor, and the shortest distance between the body of the pass transistor and the non-square conductive active region is less than the shortest distance between the bodies of the pass transistor and the driver transistor.
Technical advantages of one or more embodiments of the present invention include providing an improved SOI SRAM memory cell. Accordingly, characteristic variation between multiple memory cells is reduced, stability for the memory cell is increased, and noise margin for the memory cell is improved.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, descriptions and claims.